1. Technical Field
The present invention relates to semiconductor devices, and more particularly, to a testing method capable of detecting latent defective memory cells in a semiconductor device on which the testing method is performed.
2. Discussion of the Related Art
A semiconductor device having a plurality of memory cells cannot function properly if one of the memory cells is defective. Accordingly, various testing methods have been developed to detect defective memory cells.
Defective memory cells include defects that are easily detected because, for example, they malfunction upon testing and defects that are not as easily detected upon testing because they are latent. Memory cells that have latent defects are called “weak cells” because they function properly at present but are likely to have defects after prolonged use.
If semiconductor devices are tested to detect weak cells before they are provided to users, their reliability can be increased. One method of testing a semiconductor device to detect week cells is disclosed in U.S. Pat. No. 5,920,517, issued Jul. 6, 1999, entitled “Memory Array Test And Characterization Using Isolated Memory Cell Power Supply.”
Since tests for detecting weak cells are typically time consuming, methods to reduce the test time are desired because the test time directly relates to the cost of the test and to the cost of producing a product.